It is well known that static electricity can be produced in every day situations. Static electricity is created when electrons are transferred from one object to another, thereby negatively charging one object while positively charging the other. An electrostatic potential, either positive or negative, can be carried on the skin of a person, for example, and discharged to an object having a different electrostatic potential. When an electric field between oppositely charged objects breaks down, an electrostatic discharge (ESD), or “shock”, can occur. An ESD event is characterized by a high voltage, but the current and charge are relatively low.
As an example, when a person walks across a carpet, a voltage on the order of about 10 kilovolts (kV) can be produced. Although a discharge of such a voltage may cause only mild discomfort for the person, such a discharge can destroy semiconductor chips and other computer components, which are extremely sensitive to ESD. In fact, a discharge of a voltage as low as 10 volts, far too small to even be felt by a person, can damage semiconductor chips. For this reason, circuitry for protecting chips from destructive ESD pulses is typically designed into chips. This built-in ESD protection circuitry is intended to provide protection during the physical handling of the chip before it is actually installed on a circuit board or integrated into a larger electronic system.
FIG. 1 illustrates a portion of a conventional semiconductor chip 10. The chip 10 shown in FIG. 1 includes functional circuitry 12 for performing logic operations and a plurality of pads 14 for connection to external circuitry (not shown). Some pads 14, for example, may be reserved for connection to power or ground. Positioned between the functional circuitry 12 and the pads 14 are input/output (I/O) circuits 16. The I/O circuits 16 may include, for example, output drivers for driving the pads 14 to either a logic high value or a logic low value.
If the chip 10 were to experience an ESD pulse, the voltage discharge will usually occur at the pads 14, including the power terminal pad(s) and ground terminal pad(s) of the chip 10. For this reason, the I/O circuits 16 will experience the ESD pulse first and will typically be the weakest link in the ESD equation.
Therefore, the I/O circuits 16 may also be designed with ESD protection circuitry, in addition to the output drivers, for protecting the chip 10 and especially the output drivers. Furthermore, an output driver and ESD protection circuit can be combined in the I/O circuit 16 in such a way as to save area on the chip, which can be beneficial for reducing the chip size.
FIG. 2 illustrates a conventional I/O circuit 16 which, as mentioned with respect to FIG. 1, can be positioned between the functional circuitry 12 and the pads 14 of the chip 10. The I/O circuit 16 of FIG. 2 includes an output driver 18 and an ESD protection circuit 20. The output driver 18 and the ESD protection circuit 20 may be part of the same circuit layout structure, if desired, using an interleaved configuration to reduce the overall area.
The output driver 18 includes a PMOS transistor 22 and an NMOS transistor 24. The PMOS transistor 22 receives at its gate a gate control signal PG from the functional circuitry 12, and the NMOS transistor 24 receives a gate control signal NG at its gate. Typically, the PG and NG signals are the same. During normal operation of the output driver 18, a low input at PG and NG turns on the PMOS transistor 22 to connect the respective pad 14 to VDD and turns off the NMOS transistor 24. A high input at PG and NG turns off the PMOS transistor 22 and turns on the NMOS transistor 24 to connect the pad 14 to VSS, or ground. Therefore, this output driver 18 acts as a CMOS inverter in that a high input to PG and NG produces a low output at the pad 14 and a low input to PG and NG produces a high output at the pad 14.
ESD protection circuits may be configured using any number of conventional ESD protection schemes. The ESD protection circuit 20 shown in FIG. 2, however, includes a plurality of fingers, each finger comprising one PMOS transistor 26 and one NMOS transistor 28. The ESD protection circuit 20 may include any number of fingers, depending on the desired capacity of ESD protection. For example, the I/O circuit 16 may have twelve fingers, where one finger is used as the output driver 18 and the remaining eleven fingers are used for the ESD protection circuit 20. The amount of energy that the ESD protection circuit 20 can dissipate is proportional to the total area of its fingers. Each of the two transistors of a finger is connected at a common node, which is connected to the respective pad 14 of the chip. Each PMOS transistor 26 of the ESD protection circuit 20 is connected in parallel with the PMOS transistor 22 of the output driver 18, and each NMOS transistor 28 of the ESD protection circuit 20 is connected in parallel with the NMOS transistor 24 of the output driver 18. The gates of the PMOS transistors 26 are tied to VDD and the gates of the NMOS transistors 28 are tied to VSS, thereby making the transistors 26 and 28 of the ESD protection circuit 20 essentially invisible during normal operation of the chip. These transistors 26 and 28, however, are used to protect the chip from ESD events, especially during the handling of the chip.
As is known in the art, each CMOS transistor inherently contains a small parasitic diode. The combination of the plurality of PMOS transistors 26 of the ESD protection circuit 20 possesses a large PMOS parasitic diode 30 that shunts current in a forward-bias direction from the pad 14 to VDD. Also, the combination of the plurality of NMOS transistors 28 possesses a large NMOS parasitic diode 32 that shunts current in a forward-bias direction from VSS to the pad 14. The parasitic diodes 30 and 32 can also shunt the current in a reverse-bias direction when a breakdown voltage is reached. The PMOS parasitic diode 30 and the NMOS parasitic diode 32 are capable of dissipating the charge to protect the chip from damage caused by the ESD event. The ESD protection circuit 20 and output driver 18 may include PMOS and NMOS transistors and drain diodes that are doped such that the effective breakdown voltage is adjusted to be lower than that of the transistors and diodes residing in functional circuitry 12. When a chip is manufactured with ESD protection circuitry, the chip can be tested using methods that attempt to model real-world ESD events. For example, one test includes applying a 2 kV pulse to different terminals of the chip to check whether or not the ESD protection circuit is able to dissipate the charge. The 2 kV pulse may be applied in at least four ways: from a pad to VDD, from VDD to a pad, from a pad to VSS, and from VSS to a pad. If the chip is able to manage these four pulses, then it is considered to have acceptable ESD protection.
However, even though prior art ESD protection circuits may pass these tests and operate well in most situations, it is possible that such ESD protection circuits may still fail under certain conditions that cannot be easily repeatable. It has been proposed that one possible reason for failure may be that an ESD event may actually cause a chip to be “powered up” by the discharge. This can be caused, for example, when an ESD pulse from the pad 14 to VSS is applied causing a current to be supplied through the PMOS parasitic diode 30 to VDD, powering up the chip. If by happenstance the NG signal at the gate of the NMOS transistor 24 of the output driver 18 is high and drives transistor 24 to a conductive state when the chip is powered up, a large current may be delivered to the relatively small area of the transistor 24, causing the output driver 18 to be destroyed. This occurs because the conducting transistor 24 has a lower impedance than the other parallel devices residing in the ESD protection circuit 20. There is therefore a need in the art to provide a circuit that can provide improved ESD protection, even when an ESD event powers up the chip.